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74HC390

Philips
Part Number 74HC390
Manufacturer Philips
Description Dual decade ripple counter
Published May 28, 2005
Detailed Description INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Fam...
Datasheet PDF File 74HC390 PDF File

74HC390
74HC390

Overview
INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT390 Dual decade ripple counter Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Dual decade ripple counter FEATURES • Two BCD decade or bi-quinary counters • One package can be configured to divide-by-2, 4, 5, 10, 20, 25, 50 or 100 • Two master reset inputs to clear each decade counter individually • Output capability: standard • ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no.
7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters divided into four separately clocked sections.
The counters have two divide-by-2 sections and two divide-by-5 sections.
These sections are normally used in a BCD QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT390 decade or bi-quinary configuration, since they share a common master reset input (nMR).
If the two master reset inputs (1MR and 2MR) are used to simultaneously clear all 8 bits of the counter, a number of counting configurations are possible within one package.
The separate clocks (nCP0 and nCP1 ) of each section allow ripple counter or frequency division applications of divide-by-2, 4, 5, 10, 20, 25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of the clock inputs (nCP0 and nCP1 ).
For BCD decade operation, the nQ0 output is connected to the nCP1 input of, the divide-by-5 section.
For bi-quinary decade operation, the nQ3 output is connected to the nCP0 input and nQ0 becomes the decade output.
The master reset inputs (1MR and 2MR) are active HIGH asynchronous inputs to each decade counter which operates on ...


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