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CH7012A

ETC
Part Number CH7012A
Manufacturer ETC
Description Chrontel CH7012 TV Output Device
Published Aug 23, 2005
Detailed Description CH7012A CHRONTEL Chrontel CH7012 TV Output Device Features • TV output supporting up to 1024x768 graphics resolutions •...
Datasheet PDF File CH7012A PDF File

CH7012A
CH7012A

Overview
CH7012A CHRONTEL Chrontel CH7012 TV Output Device Features • TV output supporting up to 1024x768 graphics resolutions • Programmable digital interface supports RGB and YCrCb • TrueScaleTM rendering engine supports underscan in all TV output resolutions • Enhanced text sharpness and adaptive flicker removal with up to 7 lines of filtering • Support for all NTSC and PAL formats • Provides CVBS, S-Video and SCART (RGB) outputs • TV connection detect • Programmable power management • 10-bit video DAC outputs • Fully programmable through serial port • Complete Windows and DOS driver support • Low voltage interface support to graphics device • Offered in a 64-pin LQFP package General Description The CH7012 is a display controller device which accepts a digital graphics input signal, and encodes and transmits data to a TV output (analog composite, svideo or RGB).
The device accepts data over one 12-bit wide variable voltage data port which supports five different data formats including RGB and YCrCb.
The TV-Out processor will perform non-interlace to interlace conversion with scaling and flicker filters, and encode the data into any of the NTSC or PAL video standards.
The scaling and flicker filter is adaptive and programmable to enable superior text display.
Eight graphics resolutions are supported up to 1024 by 768 with full vertical and horizontal underscan capability in all modes.
A high accuracy low jitter phase locked loop is integrated to create outstanding video quality.
Support is provided for RGB bypass mode which enables driving a VGA CRT with the input data.
LINE MEMORY YUV-RGB CONVERTER RGB-YUV CONVERTER DIGITAL D [11:0] PIXEL DATA INPUT INTERFACE CVBS TRUE SCALE SCALING & DEFLICKERING ENGINE NTSC/PAL ENCODER & FILTERS Four 10-bit DAC’s Y/R C/G CVBS/B SYSTEM CLOCK ISET GPIO[1:0] SERIAL PORT REGISTER & CONTROL BLOCK PLL TIMING & SYNC GENERATOR SC SD RESET* XCLK/XCLK* H V XI/FIN XO CSYNC P-OUT BCO Figure 1: Functional Block Diagram 201-0000...


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