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KM48S8030C

Part Number	KM48S8030C
Manufacturer	Samsung semiconductor
Description	2M x 8Bit x 4 Banks Synchronous DRAM
Published	Sep 29, 2005
Detailed Description	KM48S8030C Revision History Revision 0.0 (Oct., 1998) • PC133 first published. Preliminary PC133 CMOS SDRAM REV. 0 Oct...
Datasheet	KM48S8030C PDF File

Overview

KM48S8030C Revision History Revision 0.
0 (Oct.
, 1998) • PC133 first published.
Preliminary PC133 CMOS SDRAM REV.
0 Oct.
'98 KM48S8030C 2M x 8Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.
3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -.
CAS latency 3 only -.
Burst length (1, 2, 4, 8 & Full page) -.
Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K Cycle) Preliminary PC133 CMOS SDRAM GENERAL DESCRIPTION The KM48S8030C is 67,108,864 bits synchronous h...

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