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MC74HC240A

ON Semiconductor
Part Number MC74HC240A
Manufacturer ON Semiconductor
Description Octal 3-State Inverting Buffer/Line Driver/Line Receiver
Published Nov 24, 2005
Detailed Description MC74HC240A Octal 3-State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS The MC74HC240A i...
Datasheet PDF File MC74HC240A PDF File

MC74HC240A
MC74HC240A

Overview
MC74HC240A Octal 3-State Inverting Buffer/Line Driver/Line Receiver High−Performance Silicon−Gate CMOS The MC74HC240A is identical in pinout to the LS240.
The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
This octal noninverting buffer/line driver/line receiver is designed to be used with 3−state memory address drivers, clock drivers, and other sub−oriented systems.
The device has inverting outputs and two active−low output enables.
The HC240A is similar in function to the HC244A.
Features • Output Drive Capability: 15 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.
0 to 6.
0 V • Low Input Current: 1 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements Defined by JEDEC Standard No.
7 A • Chip Complexity: 120 FETs or 30 Equivalent Gates • NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP Capable • These Devices are Pb−Free, Halogen Free and are RoHS Compliant LOGIC DIAGRAM A1 2 A2 4 A3 6 DATA NPUTS A4 8 B1 11 B2 13 B3 15 B4 17 18 YA1 16 YA2 14 YA3 12 YA4 9 YB1 INVERTING OUTPUTS 7 YB2 5 YB3 3 YB4 OUTPUT ENABLE A 1 ENABLES 19 ENABLE B PIN 20 = VCC PIN 10 = GND © Semiconductor Components Industries, LLC, 2014 August, 2014 − Rev.
13 1 http://onsemi.
com SOIC−20 DW SUFFIX CASE 751D TSSOP−20 DT SUFFIX CASE 948E PIN ASSIGNMENT ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 ENABLE B 18 YA1 17 B4 16 YA2 15 B3 14 YA3 13 B2 12 YA4 11 B1 MARKING DIAGRAMS 20 20 HC240A AWLYYWWG 1 HC 240A ALYWG G 1 SOIC−20 TSSOP−20 A WL, L YY, Y WW, W G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) FUNCTION TABLE Inputs Outputs Enable A, Enable B A, B YA, YB L LH LHL HXZ Z = high impedance ORDERING INFORMATION See detailed...


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