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T8208

Agere Systems
Part Number T8208
Manufacturer Agere Systems
Description ATM Interconnect
Published Jul 19, 2006
Detailed Description www.DataSheet4U.com Advance Data Sheet September 2001 CelXpresTM T8208 ATM Interconnect 1 1.1 s Product Overview Feat...
Datasheet PDF File T8208 PDF File

T8208
T8208

Overview
www.
DataSheet4U.
com Advance Data Sheet September 2001 CelXpresTM T8208 ATM Interconnect 1 1.
1 s Product Overview Features s Programmable priority for control/data cells transmission onto cell bus Microprocessor access to all headers of control cell Ability to clear counters on read Simplified looping to any system device with a single register programming UTOPIA clock sourcing with additional settings Programmable operations and maintenance and resource management (OAM/RM) cell routing Support of multicast and broadcast cells per PHY s OC-12 data throughput on UTOPIA (16-bit) (independently on RX and TX UTOPIA) Shared UTOPIA mode UTOPIA Level 1 and 2 (8-bit/16-bit) cell-level handshake interface (ATM or PHY layers) Multi-PHY (MPHY) operation Programmable ATM layer supports up to 64 PHY ports s s s s s s s s s s s s s Optional monitoring of misrouted cells Egress SDRAM buffer support to extend UTOPIA s Counters for dropped cells per queue output priority queues for 32K to 512K cells: — 128 queues configurable up to four queues per s Digital loopback before cell bus DataShee PHY with programmable sizes s Microprocessor interface, supporting both Motor— Programmable number of UTOPIA output queues with four levels of priority DataSheet4U.
com ola® and Intel ® modes (multiplexed and nonmultiplexed) Support of ATM traffic management via partial s Control cell transmission and reception through packet discard (PPD), forward explicit congestion microprocessor port notification (FECN), and the cell loss priority (CLP) bit s Single 3.
3 V power supply Programmable slew rate GTL+ I/O: s 3.
3 V TTL I/O (5 V tolerant) — Programmable as bus arbiter — 1.
7 Gbits/s cell bus operation s 272-pin plastic ball grid array (PBGA) package s s Flexible per port cell counters Cell header insertion with virtual path identifier (VPI) and virtual channel identifier (VCI) translation via external SRAM (up to 64K entries) Support of network node interface (NNI) and user network int...


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