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TC74AC164F

Toshiba Semiconductor
Part Number TC74AC164F
Manufacturer Toshiba Semiconductor
Description 8-Bit Shift Register
Published Aug 25, 2006
Detailed Description TC74AC164P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC164P, TC74AC164F, TC74AC164FT 8-Bit Shi...
Datasheet PDF File TC74AC164F PDF File

TC74AC164F
TC74AC164F

Overview
TC74AC164P/F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC164P, TC74AC164F, TC74AC164FT 8-Bit Shift Register (S-IN, P-OUT) The TC74AC164 is an advanced high speed CMOS 8-BIT SERIAL-IN PARALLEL-OUT SHIFT REGISTER fabricated with silicon gate and double-layer metal wiring C2MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation.
It consists of a serial-in, parallel-out 8-bit shift register with a CLOCK input and an overriding CLEAR input.
Two serial data inputs (A, B) are provided so that one may be used as a data enable.
All inputs are equipped with protection circuits against static discharge or transient excess voltage.
Features • High speed: fmax = 170 MHz (typ.
) at VCC = 5 V • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C • High noise immunity: VNIH = VNIL = 28% VCC (min) • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL • Wide operating voltage range: VCC (opr) = 2 V to 5.
5 V • Pin and function compatible with 74F164 TC74AC164P TC74AC164F TC74AC164FT Weight DIP14-P-300-2.
54 SOP14-P-300-1.
27A TSSOP14-P-0044-0.
65A : 0.
96 g (typ.
) : 0.
18 g (typ.
) : 0.
06 g (typ.
) Start of commercial production 1988-10 1 2014-03-01 Pin Assignment TC74AC164P/F/FT IEC Logic Symbol A1 B2 QA 3 QB 4 QC 5 QD 6 GND 7 (top view) 14 VCC 13 QH 12 QG 11 QF 10 QE 9 CLR 8 CK CLR (9) CK (8) SRG 8 R C1/ A (1) B (2) & 1D (3) QA (4) QB (5) QC (6) QD (10) QE (11) QF (12) QG (13) QH Truth Table Inputs CLR CK Serial In A B L X X X H X X H L X H X L H H H Outputs QA QB … QH L L … L No Change L QAn … QGn L QAn … QGn H QAn … QGn X: Don’t care QAn to QGn: The level of QA to QG, respectively, before the most recent positive edge of the clock.
System Diagram 9 CLR 1 A Serial Inputs 2 B 8 CK R DQ R DQ R DQ R DQ R DQ R DQ R DQ R DQ C...


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