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IDTCV119E

Part Number	IDTCV119E
Manufacturer	Integrated Device Technology
Description	CLOCK GENERATOR FOR DESKTOP PC PLATFORMS
Published	Oct 11, 2006
Detailed Description	www.DataSheet4U.com IDTCV119E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR F...
Datasheet	IDTCV119E PDF File

Overview

www.
DataSheet4U.
com IDTCV119E CLOCK GENERATOR FOR DESKTOP PC PLATFORMS COMMERCIAL TEMPERATURE RANGE CLOCK GENERATOR FOR DESKTOP PC PLATFORMS IDTCV119E FEATURES: • • • • • • • • • • • 4 PLL architecture Linear frequency programming Independent frequency programming and SSC control Band-gap circuit for differential output High power-noise rejection ratio 66MHz to 533MHz CPU frequency VCO frequency up to 1.
1G Support index block read/write, single cycle index block read Programmable REF, 3V66, PCI, 48MHz I/O drive strength Programmable 3V66 and PCI Skew Available in SSOP package IDTCV119E is a 48 pin clock generation device for desktop PC platforms.
This chip incorporates four PLLs to allow independent generation of CPU, AGP/ PCI, SRC, and 48MHz clocks.
The dedicated PLL for Serial ATA clock provides high accuracy frequency.
This device also implements Band-gap referenced IREF to reduce the impact of VDD variation on differential outputs, which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, providing high accuracy output clock.
Each CPU, AGP/PCI, SRC clock has its own Spread Spectrum selection.
DESCRIPTION: KEY SPECIFICATION: • • • • CPU/SRC CLK cycle to cycle jitter < 125ps SATA CLK cycle to cycle jitter < 125ps PCI CLK cycle to cycle jitter < 250ps Static PLL frequency divide error as low as 36 ppm FUNCTIONAL BLOCK DIAGRAM DataSheet4U.
com PLL1 SSC EasyN Programming CPU CLK Output Buffers CPU[1:0] CPU_ITP DataShee X1 XTAL Osc Amp IREF REF 1.
0 X2 PLL2 SSC EasyN Programming SDATA SCLK SM Bus Controller 3V66/PCI Output Buffers PCI[5:0], PCIF[2:0] 3V66[3:1] PLL3 SSC VTT_PWRGD Watch Dog Timer FS[1:0] Control Logic SRC CLK Output Buffer SRC IREF 48MHz[1:0] S EL24_48# PLL4 48MHz Output Buffer RESET# OUTPUT TABLE CPU (Pair) 3 3V66 3 3V66/VCH 1 PCI 6 PCIF 3 REF 2 48MHz 2 24 - 48MHz 0 SRC (Pair) 1 Reset# 1 DataSheet4U.
com The IDT logo is a registered trademark of Integrated Device Technology, Inc...

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