(CY7C1355C / CY7C1357C) 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM
Description
www.DataSheet4U.com
PRELIMINARY
CY7C1355C CY7C1357C
9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL™ Architecture
Features
No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles. Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock Pin compatible and functiona...