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TMP92C820FG

Toshiba
Part Number TMP92C820FG
Manufacturer Toshiba
Description 16-Bit Microcontroller
Published Nov 9, 2006
Detailed Description TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/H1 Series TMP92C820FG Semiconductor Company Preface Thank you ver...
Datasheet PDF File TMP92C820FG PDF File

TMP92C820FG
TMP92C820FG

Overview
TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/H1 Series TMP92C820FG Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs.
Before use this LSI, refer the section, “Points of Note and Restrictions”.
Especially, take care below cautions.
**CAUTION** How to release the HALT mode Usually, interrupts can release all halts status.
However, the interrupts = (INT0 to INT3, INTKEY, INTRTC, INTALM0 to INTALM4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 3 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case).
(In this case, an interrupt request is kept on hold internally.
) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly.
The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt.
TMP92C820 CMOS 32-bit Microcontrollers TMP92C820FG/JTMP92C820 1.
Outline and Device Characteristics TMP92C820 is high-speed advanced 32-bit microcontroller developed for controlling equipment which processes mass data.
TMP92C820 is a microcontroller which has a high-performance CPU (900/H1 CPU) and various built-in I/Os.
TMP92C820FG is housed in a 144-pin flat package.
JTMP92C820 is a 144-pad chip product.
Device characteristics are as follows: (1) CPU: 32-bit CPU (900/H1 CPU) • Compatible with TLCS-900, 900/L, 900/L1, 900/H’s instruction code • 16 Mbytes of linear address space • General-purpose register and register banks • Micro DMA: 8 channels (250 ns/4 bytes at fSYS = 20 MHz, best case) (2) Minimum instruction execution time: 50 ns (at SYS = 20 MHz) RESTRICTIONS ON PRODUCT USE • The information contained herein is subject to change without notice.
021023_D 070208EBP • TOSHIBA is continually working to improve the quality and r...


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