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Preliminary Technical Data
KEY FEATURES
500 MHz, 2.0 ns Instruction Cycle Rate 12M Bits of Internal—On-Chip—DRAM Memory 25×25 mm (576-Ball) Thermally Enhanced Ball Grid Array Package Dual Computation Blocks—Each Containing an ALU, a Multiplier, a Shifter, and a Register File Dual Integer ALUs, providing Data Addressing and Pointer Manipu...
