DatasheetsPDF.com

UPD44321181

NEC
Part Number UPD44321181
Manufacturer NEC
Description (UPD44321181 / UPD44321361) 32M-BIT ZEROSB SRAM FLOW THROUGH OPERATION
Published Nov 25, 2006
Detailed Description www.DataSheet4U.com DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321181, 44321361 32M-BIT ZEROSBTM SRAM FLOW THROUGH OPERA...
Datasheet PDF File UPD44321181 PDF File

UPD44321181
UPD44321181

Overview
www.
DataSheet4U.
com DATA SHEET MOS INTEGRATED CIRCUIT µ PD44321181, 44321361 32M-BIT ZEROSBTM SRAM FLOW THROUGH OPERATION Description The µPD44321181 is a 2,097,152-word by 18-bit and the µPD44321361 is a 1,048,576-word by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The µPD44321181 and µPD44321361 are optimized to eliminate dead cycles for read to write, or write to read transitions.
These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter and output buffer as well as SRAM core.
All input registers are controlled by a positive edge of the single clock input (CLK).
The µPD44321181 and µPD44321361 are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration, such as buffer memory.
ZZ has to be set LOW at the normal operation.
When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”).
In the “Sleep” state, the SRAM internal state is preserved.
When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD44321181 and µPD44321361 are packaged in 100-pin PLASTIC LQFP with a 1.
4 mm package thickness for high density and low capacitive loading.
Features • Low voltage core supply: VDD = 3.
3 ± 0.
165 V / 2.
5 ± 0.
125 V • Synchronous operation • 100 percent bus utilization • Internally self-timed write control • Burst read / write : Interleaved burst and linear burst sequence • Fully registered inputs and outputs for flow through operation • All registers triggered off positive clock edge • 3.
3V or 2.
5V LVTTL Compatible : All inputs and outputs • Fast clock access time : 7.
5 ns (117 MHz) • Asynchronous output enable : /G • Burst sequence selectable : MODE • Sleep mode : ZZ (ZZ = Open or Low : Normal operation) • Separate byte write enable : /BW1 to /BW4 (µPD44321361) /BW1 and /BW2 (µPD44321181) • Three chip enables for easy depth expansion • Common I/O using three state outputs The inform...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)