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QL16x24B pASIC® 1 Family Very-High-Speed CMOS FPGA
Rev C pASIC HIGHLIGHTS Very High Speed – ViaLink® metal-to-metal programmable–via antifuse technology, allows counter speeds over 150 MHz and logic cell delays of under 2 ns. High Usable Density – A 16-by-24 array of 384 logic cells provides 4,000 usable ASIC gates (7,000 PLD gates) in 8...
