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T7502

Agere Systems
Part Number T7502
Manufacturer Agere Systems
Description Dual PCM Codec
Published Dec 20, 2006
Detailed Description www.DataSheet4U.com Data Sheet February 1998 T7502 Dual PCM Codec with Filters Features s s s s Applications s s s +...
Datasheet PDF File T7502 PDF File

T7502
T7502

Overview
www.
DataSheet4U.
com Data Sheet February 1998 T7502 Dual PCM Codec with Filters Features s s s s Applications s s s +5 V only Automatic powerdown mode Low-power, latch-up-free CMOS technology On-chip sample and hold, autozero, and precision voltage reference Differential architecture for high noise immunity and power supply rejection Automatic master clock frequency selection 2.
048 MHz or 4.
096 MHz fixed data rate Frame sync controlled channel swapping Differential analog I/O 300 Ω output drivers Operating temperature range: –40 °C to +85 °C A-law companding Speakerphone Telephone answering device (TAD) POTS for ISDN Description The T7502 device is a single-chip, two-channel A-law PCM codec with filters.
This integrated circuit provides analog-to-digital and digital-to-analog conversion.
It provides the transmit and receive filtering necessary to interface a voice telephone circuit to a time-division multiplexed (TDM) system.
The device features a differential transmit amplifier, and the power receive amplifier is capable of driving 600 Ω differentially.
PCM timing is defined by a single frame sync pulse.
This device operates in a delayed timing mode (digital data is valid one clock cycle after frame sync goes high).
The T7502 is packaged in a 20-pin SOJ.
s s s s s s s s GSX0 DX VFXIN0 VFXIP0 VCM0 – + +2.
4 V FILTER NETWORK ENCODER PCM INTERFACE DR GNDD CHANNEL 0 FS VFROP0 VFRON0 FILTER NETWORK DECODER POWERDOWN CONTROL INTERNAL TIMING & CONTROL GSX1 VFXIN1 VFXIP1 VCM1 VFROP1 VFRON1 CHANNEL 1 BIAS CIRCUITRY & REFERENCE VDD (1) GNDA (2) MCLK 5-3609.
b Figure 1.
Block Diagram T7502 Dual PCM Codec with Filters Data Sheet February 1998 Functional Description The T7502 has one frame sync (FS) input that determines transmit and receive data timing for both channels.
The width of the FS pulse determines the order of the two channels on the PCM buses.
If FS is nominally one MCLK period wide (see Figure 5), the data for channel 0 is first.
If FS is nominally two or more...


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