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EPXA4

Altera Corporation
Part Number EPXA4
Manufacturer Altera Corporation
Description Excalibur Devices
Published Dec 23, 2006
Detailed Description www.DataSheet4U.com Excalibur EPXA4 Devices November 2002, ver. 1.2 Errata Sheet This errata sheet provides updated ...
Datasheet PDF File EPXA4 PDF File

EPXA4
EPXA4

Overview
www.
DataSheet4U.
com Excalibur EPXA4 Devices November 2002, ver.
1.
2 Errata Sheet This errata sheet provides updated information about the Excalibur™ EPXA4, revision A (see Figure 1) Devices.
Figure 1.
Identify Revision A Devices Revision Number The errata fall into two categories: ■ ■ Known errata for the EPXA4 device—detailed in this document Known errata for the ARM922T processor provided by ARM Ltd.
— detailed in Appendix A of this document The following sections of the device are covered by errata information: ■ ■ ■ ■ ■ ■ ■ ■ Expansion bus interface (EBI) Dual-port SRAM (DPRAM) AHB bridges UART SDRAM Embedded trace module version 2a Configuration Debug module Contact Altera® for the latest information.
Altera Corporation ES-EPXA4-1.
2 1 Excalibur EPXA4 Devices Errata Sheet EBI 1.
1 This section provides further information about errata in the EBI.
Locked 16-Beat Incrementing Bursts A locked INCR16 transfer can cause the EBI to read from a peripheral twice.
This can cause erroneous behavior if the peripheral contains readsensitive registers.
Work Around Do not use burst transactions to access read-sensitive peripherals connected to the EBI.
1.
2 EBI Acknowledge Signal The EBI acknowledge signal, EBI_ACK, functionality results in incorrect EBI asynchronous mode operation.
Work Around Do not use the EBI_ACK signal when interfacing to external memory devices.
Instead, use the programmable wait states, via the EBI_BLOCKn register, for the individual EBI blocks.
Also ensure that the SA bit for each EBI block is cleared.
This effectively puts the EBI in synchronous mode.
EBI synchronous mode can be used to interface with synchronous or asynchronous memories provided that the appropriate number of wait states is implemented.
DPRAM 2.
1 This section provides further information about errata in the DPRAM.
Port A Clocks Are Not Pre-Balanced If the DPRAM is configured in either a deep (×8) or a wide (×32) mode, the dp0_2_portaclk and dp1_3_portaclk clock sig...


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