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ADATE205

Analog Devices
Part Number ADATE205
Manufacturer Analog Devices
Description Dual DCL
Published Jan 8, 2007
Detailed Description www.DataSheet4U.com 250 MHz Dual DCL ADATE205 FEATURES Driver, comparator, and active load 250 MHz toggle rate Inhibit ...
Datasheet PDF File ADATE205 PDF File

ADATE205
ADATE205

Overview
www.
DataSheet4U.
com 250 MHz Dual DCL ADATE205 FEATURES Driver, comparator, and active load 250 MHz toggle rate Inhibit mode function Dynamic clamps Operating voltage range: −1.
5 V to +6.
5 V Output voltage swing: 200 mV to 8 V Four range adjustable slew rate True/complement data mode bit 100-lead thin quad flat package, exposed pad Low per channel power 1.
15 W with load off 1.
50 W with load programmed at 20 mA nominal Low leakage (<10 nA) in High-Z mode Driver 50 Ω output resistance 1.
6 ns minimum pulse width for a 3 V step Load: −35 mA to +35 mA maximum current range 7 69 8 68 9 67 6 70 22 54 23 53 24 52 25 51 26 50 27 49 28 48 29 47 15 61 14 62 10 65 11 66 FUNCTIONAL BLOCK DIAGRAM VCC (18, 19, 57, 58, 77, 78, 89, 98, 99) NC (30, 46) SHIELDS (80, 82, 94, 96) VIT VIL VIH ADATE205 DR_INV DR_DATA_P DR_DATA_P_T DR_DATA_N_T DR_DATA_N DR_EN_P DR_EN_P_T DR_EN_N_T DR_EN_N VTEN LDEN CLAMPL CLAMPH LOGIC DRIVER 81 95 DUT APPLICATIONS Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment CVH COMP_H_P COMP_H_N CLLM COMP_L_P COMP_L_N CVL 91 85 31 45 32 44 13 63 34 42 35 41 90 86 COMP_H GENERAL DESCRIPTION The ADATE205 is a complete, single-chip solution that performs the pin electronics functions of driver, comparator, and active load (DCL) for ATE applications.
The active load can be powered down if not used.
The driver is a proprietary design that features three active modes: data high mode, data low mode, and term mode, as well as an inhibit state.
The driver has low leakage (<10 nA) in High-Z mode.
The output voltage range is −1.
5 V to +6.
5 V to accommodate a wide variety of test devices.
The ADATE205 supports four programmable Tr/Tf times for applications where slower edge rates are required.
The edge rate selection is done via two static digital CMOS select bits.
The input data to the driver can be inverted using a single CMOS logic bit.
This feature can be used for system calibration or applicati...


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