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ADSP-BF538F

Analog Devices
Part Number ADSP-BF538F
Manufacturer Analog Devices
Description Blackfin Embedded Processor
Published Jan 16, 2007
Detailed Description www.DataSheet4U.com a FEATURES Preliminary Technical Data Up to 500 MHz high performance Blackfin processor Two 16-bit...
Datasheet PDF File ADSP-BF538F PDF File

ADSP-BF538F
ADSP-BF538F

Overview
www.
DataSheet4U.
com a FEATURES Preliminary Technical Data Up to 500 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler friendly support Advanced debug, trace, and performance monitoring 0.
8 V to 1.
2 V core VDD with on-chip voltage regulation 3.
3 V tolerant I/O with specific 5 V tolerant pins 316-ball Pb-free mini-BGA package Blackfin® Embedded Processor ADSP-BF538/ADSP-BF538F Memory management unit providing memory protection External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI® and external memory PERIPHERALS Parallel peripheral interface (PPI/GPIO) supporting ITU-R 656 video data formats Four dual-channel, full-duplex synchronous serial ports, supporting 16 stereo I2S® channels Two DMA controllers supporting 26 DMA channels Controller area network (CAN) 2.
0B controller Three SPI-compatible ports Three timer/counters with PWM support Three UARTs with support for IrDA® Two TWI controllers compatible with I2C® industry standard Up to 54 general-purpose I/O pins (GPIO) Real time clock, watchdog timer, and core timer On-chip PLL capable of 0.
5x To 64x frequency multiplication Debug/JTAG interface MEMORY 148K bytes of on-chip memory: 16K bytes of instruction SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K bytes or 1M byte of flash memory (ADSP-BF538F parts only) Four dual-channel memory DMA controllers VOLTAGE REGULATOR JTAG TEST AND EMULATION PERIPHERAL ACCESS BUS TWI0-1 CAN 2.
0B B L1 INSTRUCTION MEMORY DMA CORE BUS 1 INTERRUPT CONTROLLER PERIPHERAL ACCESS BUS WATCHDOG TIMER RTC PPI TIMER0-2 GPIO PORT F GPIO PORT C GPIO SPI1-2 UART1-2 DMA CONTROLLER1 L1 DATA MEMORY DMA CORE BUS 0 DMA ACCESS BUS 0 GPIO PORT D DMA ACCESS BUS 1 SPI0 UART0 SPORT0-1 GPIO PORT E SPORT2-3 E...


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