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74AUP1G240
Low-power inverting buffer/line driver; 3-state
Rev. 01 — 6 November 2006 Product data sheet
1. General description
The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Schmitt-trigger action at all inputs makes the circuit tolerant to slowe...
