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NB4L52

Differential Data/Clock D Flip-Flop

Description

NB4L52 2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi−Level Inputs to LVPECL Translator w/ Internal Termination The NB4L52 is a differential Data and Clock D flip−flop with a differential asynchronous Reset. The differential inputs incorporate internal 50 W termination resistors and will accept PECL, LVPECL, LVCMOS, LVTTL, CML, or LVD...

ON Semiconductor

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