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AZP92

Arizona Microtek
Part Number AZP92
Manufacturer Arizona Microtek
Description Clock Generation Chip
Published Sep 17, 2007
Detailed Description www.DataSheet4U.com ARIZONA MICROTEK, INC. AZP92 ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable FEATURES...
Datasheet PDF File AZP92 PDF File

AZP92
AZP92

Overview
www.
DataSheet4U.
com ARIZONA MICROTEK, INC.
AZP92 ECL/PECL ÷1, ÷2 Clock Generation Chip with Selectable Enable FEATURES • • • • • • • • Green and RoHS Compliant / Lead (Pb) Free Package Available 3.
0V to 5.
5V Operation Selectable Divide Ratio Selectable Enable Polarity and Threshold (CMOS/TTL or PECL) Selectable Input Biasing High Bandwidth for ≥1GHz Available in a MLP 8 (2x2) Package IBIS Model File Available on Arizona Microtek Website PACKAGE MLP 8 (2x2) Green / RoHS Compliant / Lead (Pb) Free DIE 1 2 3 4 PACKAGE AVAILABILITY PART NO.
AZP92NAG AZP92X MARKING P1G N/A NOTES 1,2 3,4 Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.
5K parts) Tape & Reel.
Date code format: “Y” for year followed by “WW” for week.
Waffle Pack Contact factory for availability DESCRIPTION The AZP92 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function.
The divide ratio is selected with the DIV-SEL pin/pad.
When DIV-SEL is open (NC), the AZP92 functions as a standard receiver.
If DIV-SEL is connected to VEE, it functions as a ÷2 divider.
A selectable enable is provided which also functions as a reset when the ÷2 mode is selected.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20kΩ resistor.
Leaving EN-SEL open or connecting it to VEE will select the EN pin/pad to function as an active high CMOS/TTL enable.
When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the outputs whenever EN is left open.
When EN-SEL is connected to VEE, an internal 75kΩ pull-down resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will select the EN pin/pad to function as an active low PECL/ECL enable with an internal 75kΩ pull-down resistor.
In this mode, outputs are enabled when EN is left open (NC).
This default logic condition can be overridden by connecting th...


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