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V58C2512804SB

Part Number	V58C2512804SB
Manufacturer	ProMOS Technologies
Description	High Performance 512M-Bit DDR SDRAM
Published	Oct 19, 2007
Detailed Description	www.DataSheet4U.com V58C2512(804/404/164)SB HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32...
Datasheet	V58C2512804SB PDF File

Overview

www.
DataSheet4U.
com V58C2512(804/404/164)SB HIGH PERFORMANCE 512 Mbit DDR SDRAM 4 BANKS X 16Mbit X 8 (804) 4 BANKS X 32Mbit X 4 (404) 4 BANKS X 8Mbit X 16 (164) 5 DDR400 Clock Cycle Time (tCK2.
5) Clock Cycle Time (tCK3) System Frequency (fCK max) 6ns 5ns 200 MHz 6 DDR333 6ns 166 MHz 75 DDR266 7.
5ns 133 MHz Features ■ High speed data transfer rates with system frequency up to 200MHz ■ Data Mask for Write Control ■ Four Banks controlled by BA0 & BA1 ■ Programmable CAS Latency: 2.
5, 3 ■ Programmable Wrap Sequence: Sequential or Interleave ■ Programmable Burst Length: 2, 4, 8 for Sequential Type 2, 4, 8 for Interleave Type ■ Automatic and Controlled Precharge Command ■ Power Down Mode ■ Auto Refresh and Self Refresh ■ Refresh Interval: 8192 cycles/64 ms ■ Available in 60 Ball FBGA AND 66 Pin TSOP II ■ SSTL-2 Compatible I/Os ■ Double Data Rate (DDR) ■ Bidirectional Data Strobe (DQS) for input and output data, active on both edges ■ On-Chip DLL aligns DQ and DQs transitions with CK transitions ■ Differential clock inputs CK and CK ■ Power Supply 2.
5V ± 0.
2V ■ Power Supply 2.
6V ± 0.
1V for DDR400 ■ tRAS lockout supported ■ Concurrent auto precharge option is supported *Note: (-5) Supports PC3200 module with 3-3-3 timing (-6) Supports PC2700 module with 2.
5-3-3 timing (-75) Supports PC2100 module with 2.
5-3-3 timing Description The V58C2512(804/404/164)SB is a four bank DDR DRAM organized as 4 banks x 16Mbit x 8 (804), 4 banks x 32Mbit x 4 (404), 4 banks x 8Mbit x 16 (164).
The V58C2512(804/404/164)SB achieves high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock.
All of the control, address, circuits are synchronized with the positive edge of an externally supplied clock.
I/O transactions are occurring on both edges of DQS.
Operating the four memory banks in an interleaved fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs.
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V58C2512804SB High Performance 512M-Bit DDR SDRAM - ProMOS Technologies

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