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HYB25D512160CF

Qimonda
Part Number HYB25D512160CF
Manufacturer Qimonda
Description (HYB25D512xx0Cx) DDR SDRAM
Published Jul 11, 2008
Detailed Description September 2006 HYB25D512400C[E/T/F/C](L) HYB25D512800C[E/T/F/C](L) HYB25D512160C[E/T/F](L) www.DataSheet4U.com DDR SDR...
Datasheet PDF File HYB25D512160CF PDF File

HYB25D512160CF
HYB25D512160CF

Overview
September 2006 HYB25D512400C[E/T/F/C](L) HYB25D512800C[E/T/F/C](L) HYB25D512160C[E/T/F](L) www.
DataSheet4U.
com DDR SDRAM RoHS Compliant Products Internet Data Sheet Rev.
1.
31 Internet Data Sheet HYB25D512[400/160/800]C[E/T/F/C](L) 512-Mbit Double-Data-Rate SDRAM HYB25D512400C[E/T/F/C](L), HYB25D512800C[E/T/F/C](L), HYB25D512160C[E/T/F](L) Revision History: 2006-09, Rev.
1.
31 Page www.
DataSheet4U.
com Subjects (major changes since last revision) Qimonda update Adapted internet edition All All Previous Revision: 2006-05, Rev.
1.
3 10 10 Added the components HYB25D512160CT-6, HYB25D512160CT-5, HYB25D512800CFL-6 HYB25D512800CFL-5, HYB25D512160CFL-6 Correct the name HYB25D512400CFL-6 Previous Revision: 2006-03, Rev.
1.
2 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to: techdoc@qimonda.
com qag_techdoc_rev400 / 3.
2 QAG / 2006-08-07 03292006-3TFJ-HNV3 2 Internet Data Sheet HYB25D512[400/160/800]C[E/T/F/C](L) 512-Mbit Double-Data-Rate SDRAM 1 www.
DataSheet4U.
com Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics.
1.
1 Features • • • • • • • • • • • • Burst Lengths: 2, 4, or 8 CAS Latency: 2, 2.
5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP=tRCD 7.
8 µs Maximum Average Periodic Refresh Interval 2.
5 V (SSTL_2 compatible) I/O VDDQ = 2.
5 V ± 0.
2 V VDD = 2.
5 V ± 0.
2 V P-TFBGA-60-11 package P-TSOPII-66-1 package RoHS Compliant Products1) • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver • DQS is edge-aligned with data for reads and is centeraligned with data for writes • ...


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