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IS61NVP10018

ISSI
Part Number IS61NVP10018
Manufacturer ISSI
Description (IS61NVP10018 / IS61NVP51236) State Bus SRAM
Published Jul 12, 2008
Detailed Description IS61NVP51236 IS61NVP10018 512K x 36 and 1M x 18 PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization...
Datasheet PDF File IS61NVP10018 PDF File

IS61NVP10018
IS61NVP10018

Overview
IS61NVP51236 IS61NVP10018 512K x 36 and 1M x 18 PIPELINE 'NO WAIT' STATE BUS SRAM FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle www.
DataSheet4U.
com • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining for TQFP • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 119 PBGA package • VDD +2.
5V power supply (± 5%) • VDDQ: 2.
5V I/O Supply Voltage • Indus...


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