DatasheetsPDF.com

DFPMUL

Part Number	DFPMUL
Manufacturer	Digital Core Design
Description	Floating Point Pipelined Multiplier Unit
Published	Nov 9, 2008
Detailed Description	DFPMUL www.DataSheet4U.com Floating Point Pipelined Multiplier Unit ver 2.70 OVERVIEW ● Fully synthesizable, static syn...
Datasheet	DFPMUL PDF File

Overview

DFPMUL www.
DataSheet4U.
com Floating Point Pipelined Multiplier Unit ver 2.
70 OVERVIEW ● Fully synthesizable, static synchronous design with no internal tri-states The DFPMUL uses the pipelined mathematics algorithm to multiply two arguments.
The input numbers format is according to IEEE754 standard.
DFPMUL supports single precision real number.
Multiply operation was pipelined up to 7 levels.
Input data are fed every clock cycle.
The first result appears after latency depending on pipeline level and next results are available each clock cycle.
Full IEEE-754 precision and accuracy were included.
DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and ALTERA’s Megafun...

Similar Datasheet

DFPMU Floating Point Coprocessor - Digital Core Design
DFPMU-DP Floating Point Coprocessor Double Precision - Digital Core Design
DFPMUL Floating Point Pipelined Multiplier Unit - Digital Core Design

Since 2006. D4U Semicon,
Electronic Components Datasheet Search Site. (Privacy Policy & Contact)