August 2004 rev 2.0
DDR 24-Bit to 48-Bit Registered Buffer
ASM4SSTVF32852
Features
Differential clock signals. Supports SSTL_2 class II specifications on inputs and outputs. Low voltage operation. VDD = 2.3V to 2.7V.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held at a logic “Low” leve...
