Universal Synchronous EPLD
Description
1CY 7C33 5
fax id: 6018
CY7C335
www.DataSheet4U.com
Universal Synchronous EPLD
Features
100-MHz output registered operation Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock select multiplexer — Feed back multiplexer — Output enable (OE) multiplexer Bypass on input and output r...
Cypress Semiconductor
CY7C335 PDF File
Similar Datasheet