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April 1999
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Features
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Description
Generates up to eighteen low-skew, non-inverting clocks from one clock input Supports up to four SDRAM DIMMs 2 Uses either I C™-bus or SMBus serial interface with Read and Write capability for individual clock output control Output enable pin tristates all clock outputs to facilitate board testing Clock outputs skew-matched to less than 250ps Less than 5ns propagation delay Output impedance: 17Ω at 0. 5VDD Serial interface I/O meet I C specifications; all other I/O are LVTTL/LVCMOS-compatible Five differerent pin configurations available:
• • • • FS6050: 18 clock outputs in a 48-pin SSOP FS6051: 10 clock outputs in a 28-pin SOIC, SSOP FS6053: 13 clock outputs in a 28-pin SOIC FS6054: 14 clock outputs in a 28-pin SOIC
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The FS6050 family of CMOS clock fanout buffer ICs are designed for high-speed motherboard appli...
FS6054 PDF File
