DatasheetsPDF.com

ADAS1128

Analog Devices
Part Number ADAS1128
Manufacturer Analog Devices
Description 24-bit Current To Digital ADC
Published Jul 18, 2009
Detailed Description www.DataSheet4U.com 128 Channel, 24-bit Current to Digital ADC ADAS1128 GENERAL DESCRIPTION The ADAS1128 is a 128-Chann...
Datasheet PDF File ADAS1128 PDF File

ADAS1128
ADAS1128

Overview
www.
DataSheet4U.
com 128 Channel, 24-bit Current to Digital ADC ADAS1128 GENERAL DESCRIPTION The ADAS1128 is a 128-Channel, current to digital analog-todigital converter ADC.
It contains 128 low power, low noise, low input current integrators, simultaneous sample-holds and two high speed, high resolution ADCs with configurable sampling rate and resolution up to 24 bits.
All converted channel results are output on a single LVDS selfclocked serial interface reducing external hardware.
An SPI-compatible serial interface allows configuration of the ADC using the SDI input.
The SDO output allows one to daisy chain several ADCs on a single, 3-wire bus.
It uses the separate supply VIO to reduce digital noise effect on the conversions.
The ADAS1128 is housed in a mini-BGA package, 10mm by 10mm.
Preliminary Technical Data FEATURES 128 Channel low level currents- to-digital converter Up to 24 bit resolution Up to 20ksps (50μs integration time) Simultaneous Sampling Ultra Low noise ( down to 0.
4fC (2500e-) ) User adjustable full-scale range INL: ±0.
025% of Reading ±1ppm of FSR Very Low Power dissipation: 4.
5 mW/channel LVDS/CMOS self-clocked serial interface Daisy-chain Configuration registers On-Board Temperature Sensor and Reference Buffer Mini-BGA package 10mm × 10mm Low-cost external components APPLICATIONS CT Scanner Data Acquisition Photodiode Sensors and Power Monitoring Spectroscopy High Channel Count Data Acquisition Systems (current or voltage input) SUPPORT TOOLS Evaluation Board Reference Design with reference layout (3 layers) FPGA Verilog Code FUNCTIONAL BLOCK DIAGRAM BUFPL BUFNL 2.
5V 3.
3V to next SDI SDO F AN0 OR0 F AN63 S/H OR63 F AN64 S/H OR64 F S/H KGND OR127 VT BUFPH BUFNH REF 2.
048V + ADCH Temp OR(0:127) Data Processing LVDS/CMOS Interface + ADCL SDI S/H REF Configuration SCK CS to all ADCs RESET DOUT CLK SYNC IOVDD IOGND 2.
5V FPGA VIO AN127 SDI SDI from previous SDO from DOUT of other ADCs Figure 1.
General Block Diagram For more information ...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)