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MAX3629

Maxim Integrated Products
Part Number MAX3629
Manufacturer Maxim Integrated Products
Description Precision Clock Generator
Published Aug 2, 2009
Detailed Description 19-4467; Rev 0; 2/09 www.DataSheet4U.com +3.3V, Low-Jitter, Precision Clock Generator with Multiple Outputs General De...
Datasheet PDF File MAX3629 PDF File

MAX3629
MAX3629

Overview
19-4467; Rev 0; 2/09 www.
DataSheet4U.
com +3.
3V, Low-Jitter, Precision Clock Generator with Multiple Outputs General Description The MAX3629 is a low-jitter precision clock generator optimized for network applications.
The device integrates a crystal oscillator and a phase-locked loop (PLL) to generate high-frequency clock outputs for Ethernet applications.
Maxim’s proprietary PLL design features ultra-low jitter (0.
4psRMS) and excellent power-supply noise rejection (PSNR), minimizing design risk for network equipment.
The MAX3629 contains five LVDS outputs and three LVCMOS outputs.
The output frequencies are selectable among 125MHz, 156.
25MHz, and 312.
5MHz by pin control.
♦ Crystal Oscillator Interface: 25MHz ♦ OSC_IN Interface: PLL Enabled: 25MHz PLL Disabled: 20MHz to 320MHz ♦ Outputs: One LVDS Output at 125MHz/156.
25MHz/ 312.
5MHz (Selectable with FSELA) Four LVDS Outputs at 125MHz/156.
25MHz/ 312.
5MHz (Selectable with FSELB) Three LVCMOS Outputs at 125MHz/156.
25MHz (Selectable with FSELB) ♦ Low Phase Jitter: 0.
4psRMS (12kHz to 20MHz) ♦ Excellent PSNR ♦ Operating Temperature Range: 0°C to +70°C Features MAX3629 Applications Ethernet Networking Equipment Typical Operating Circuit +3.
3V ±5% Ordering Information PART TEMP RANGE 0°C to +70°C PIN-PACKAGE 32 TQFN-EP* MAX3629CTJ+ 10.
5Ω 0.
1μF 0.
1μF 0.
1μF 10μF VDDA 0.
01μF VDD VDDO_DIFF VDDO_SE Q0 Z0 = 50Ω 125MHz/156.
25MHz/ 312.
5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.
25MHz/ 312.
5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.
25MHz/ 312.
5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.
25MHz/ 312.
5MHz Z0 = 50Ω Z0 = 50Ω 125MHz/156.
25MHz/ 312.
5MHz Z0 = 50Ω +Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
100Ω ASIC Q0 Pin Configuration VDDO_SE OSC_IN MAX3629 33pF X_OUT 25MHz (CL = 18pF) X_IN 27pF Q1 TOP VIEW GND Q7 Q6 Q2 24 100Ω ASIC 23 22 21 20 19 18 Q5 17 16 15 14 13 FSELB RESERVED Q4 Q4 VDDO_DIFF Q3 Q3 GND Q2 VDDA 25 PLL_BP 26 100Ω ASIC Q3 VDD PLL_BP Q3 VDD 27 FSELA 28 OSC_IN 29 MAX3629 GND 12 11 10 9 8...


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