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H5TQ2G43AFR-xxC

Hynix Semiconductor
Part Number H5TQ2G43AFR-xxC
Manufacturer Hynix Semiconductor
Description 2Gb DDR3 SDRAM
Published Mar 16, 2010
Detailed Description 2Gb DDR3 SDRAM www.DataSheet4U.com 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G43AFR-xxC H5TQ2G83AFR...
Datasheet PDF File H5TQ2G43AFR-xxC PDF File

H5TQ2G43AFR-xxC
H5TQ2G43AFR-xxC

Overview
2Gb DDR3 SDRAM www.
DataSheet4U.
com 2Gb DDR3 SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TQ2G43AFR-xxC H5TQ2G83AFR-xxC * Hynix Semiconductor reserves the right to change products or specifications without notice.
Rev.
1.
0 / Dec.
2009 1 www.
DataSheet4U.
com Revision History Revision No.
0.
01 0.
02 0.
1 1.
0 History Initial Release Added IDD Specification Datasheet version changed JEDEC Update Draft Date Feb.
2009 Apr.
2009 Aug.
2009 Dec.
2009 Remark Rev.
1.
0 / Dec.
2009 2 www.
DataSheet4U.
com Description The H5TQ2G43AFR-xxC, H5TQ2G83AFR-xxC are a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth.
Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information FEATURES • VDD=VDDQ=1.
5V +/- 0.
075V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 and (11) supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7, 8 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refresh Cycle (Tcase of 0 oC~ 95 oC) - 7.
8 µs at 0oC ~ 85 oC - 3.
9 µs at 85oC ~ 95 oC • Auto Self Refresh supported • JEDEC ...


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