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IS61VPD51236A

Part Number	IS61VPD51236A
Manufacturer	Integrated Silicon Solution
Description	512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM
Published	Apr 24, 2010
Detailed Description	IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE...
Datasheet	IS61VPD51236A PDF File

Overview

IS61VPD51236A IS61VPD102418A IS61LPD51236A IS61LPD102418A 512K x 36, 1024K x 18 18Mb SYNCHRONOUS PIPELINED, DOUBLE CYCLE DESELECT STATIC RAM www.
DataSheet4U.
com ISSI ® FEBRUARY 2006 FEATURES • Internal self-timed write cycle • Individual Byte Write Control and Global Write • Clock controlled, registered address, data and control • Burst sequence control using MODE input • Three chip enable option for simple depth expansion and address pipelining • Common data inputs and data outputs • Auto Power-down during deselect • Double cycle deselect • Snooze MODE for reduced-power standby • JTAG Boundary Scan for PBGA package • Power Supply LPD: VDD 3.
3V + 5%, VDDQ 3.
3V/2.
5V + 5% VPD: VDD 2.
5V + 5%, VDDQ 2.
5V + 5% • JEDEC 100-Pin TQFP and 165-pin PBGA package • Lead-free available DESCRIPTION The ISSI IS61LPD/VPD51236A and IS61LPD/ VPD102418A are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications.
The IS61LPD/VPD51236A is organized as 524,288 words by 36 bits, and the IS61LPD/VPD102418A is organized as 1,048,576 words by 18 bits.
Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit.
All synchronous inputs pass through registers controlled by a positiveedge-triggered single clock input.
Write cycles are internally self-timed and are initiated by the rising edge of the clock input.
Write cycles can be one to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte write enable (BWE) input combined with one or more individual byte write signals (BWx).
In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls.
Bursts can be initiated with either ADSP (Address Status Processor) o...

Similar Datasheet

IS61VPD51236A 512K x 36 - 1024K x 18 18Mb SYNCHRONOUS PIPELINED DOUBLE CYCLE DESELECT STATIC RAM - Integrated Silicon Solution
IS61VPD51236A 512K x 36/ 1024K x 18 18Mb SYNCHRONOUS PIPELINED / DOUBLE CYCLE DESELECT STATIC RAM - Integrated Silicon Solution

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