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ADC1412D080

NXP Semiconductors
Part Number ADC1412D080
Manufacturer NXP Semiconductors
Description (ADC1412D065 - ADC1412D125) Dual 14-bit ADC
Published Jun 9, 2010
Detailed Description ADC1412D065/080/105/125 Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev. 02 — 4 June 2009 ...
Datasheet PDF File ADC1412D080 PDF File

ADC1412D080
ADC1412D080

Overview
ADC1412D065/080/105/125 Dual 14-bit ADC 65, 80, 105 or 125 Msps CMOS or LVDS DDR digital outputs Rev.
02 — 4 June 2009 www.
DataSheet4U.
com Objective data sheet 1.
General description The ADC1412D is a dual channel 14-bit Analog-to-Digital Converter (ADC) optimized for high dynamic performances and low power consumption at sample rates up to 125 Msps.
Pipelined architecture and output error correction ensure the ADC1412D is accurate enough to guarantee zero missing codes over the entire operating range.
Supplied from a single 3 V source, it can handle output logic levels from 1.
8 V to 3.
3 V in CMOS mode, thanks to a separate digital output supply.
It supports the LVDS (Low Voltage Differential Signalling) DDR (Double Data Rate) output standard.
An integrated SPI (Serial Peripheral Interface) allows the user to easily configure the ADC.
The device also includes a programmable gain amplifier with a flexible input voltage range.
With excellent dynamic performance from the baseband to input frequencies of 170 MHz or more, the ADC1412D is ideal for use in communications, imaging and medical applications.
1.
5 005aaa040 1.
5 005aaa041 0 dB 005aaa042 1 1 -40 0.
5 0.
5 0 0 -80 -0.
5 -0.
5 -1 -1 -120 -1.
5 0 4000 8000 12000 16000 -1.
5 0 4000 8000 12000 16000 0 10 20 30 f (MHz) 40 Fig 1.
Integral Non-Linearity (INL) Fig 2.
Differential Non-Linearity (DNL) Fig 3.
Output spectrum: −1 dBFS, 80 Msps, fi = 4.
43 MHz 2.
Features I I I I I I SNR, 73 dB SFDR, 90 dBc Sample rate up to 125 Msps Dual-channel14-bit pipelined ADC core Single 3 V supply Flexible input voltage range: 1 V to 2 V (p-p) with 6 dB programmable fine gain I CMOS or LVDS DDR digital outputs I INL ±1 LSB, DNL ±0.
5 LSB (typical) I I I I I I Input bandwidth, 650 MHz Power dissipation, 775 mW at 80 Msps SPI Interface Duty cycle stabilizer Fast OTR detection Offset binary, 2’s complement, gray code I Power-down and Sleep modes I HVQFN64 package NXP Semiconductors ADC1412D065/080/105/125 Dual 14-bi...


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