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DS99R101

National Semiconductor
Part Number DS99R101
Manufacturer National Semiconductor
Description (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer
Published Jun 18, 2010
Detailed Description DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2007 www.DataSheet4U.com DS99R1...
Datasheet PDF File DS99R101 PDF File

DS99R101
DS99R101


Overview
DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2007 www.
DataSheet4U.
com DS99R101/DS99R102 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer General Description The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths.
It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS99R101/DS99R102 incorporates LVDS signaling on the high-speed I/O.
LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path.
By optimizing the serializer output edge rate for the operating frequency range EMI is further reduced.
Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
■ Internal DC Balancing encode/decode – Supports AC■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Features ■ 3 MHz–40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions Transmitter and Receiver ■ User selectable clock edge for parallel data on both coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random data lock) to support livepluggable applications LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects All LVCMOS inputs and control pins have internal pulldown On-chip filters for PLLs on Transmitter and Receiver 48-pin TQFP package Pure CMOS .
35 μm process Power supply range 3.
3V ± 10% Temperature range 0°C to +70°C 8 kV HBM ESD tol...



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