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DAC1008D750

NXP Semiconductors
Part Number DAC1008D750
Manufacturer NXP Semiconductors
Description Dual 10-bit DAC
Published Dec 4, 2010
Detailed Description DAC1008D750 Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface Rev. 01 — 4 October 2010...
Datasheet PDF File DAC1008D750 PDF File

DAC1008D750
DAC1008D750

Overview
DAC1008D750 Dual 10-bit DAC; up to 750 Msps; 2×, 4× or 8× interpolating with JESD204A interface Rev.
01 — 4 October 2010 Objective data sheet 1.
General description The DAC1008D750 is a high-speed 10-bit dual channel Digital-to-Analog Converter (DAC) with selectable 2×, 4× or 8× interpolating filters optimized for multi-carrier WCDMA transmitters.
Because of its digital on-chip modulation, the DAC1008D750 allows the complex pattern provided through lane 0, lane 1, lane 2 and lane 3, to be converted up from baseband to IF.
The mixing frequency is adjusted via a Serial Peripheral Interface (SPI) with a 32-bit Numerically Controlled Oscillator (NCO) and the phase is controlled by a 16-bit register.
The DAC1008D750 also includes a 2×, 4× or 8× clock multiplier which provides the appropriate internal clocks and an internal regulation to adjust the output full-scale current.
The input data format is serial according to JESD204A specification.
This new interface has numerous advantages over the traditional parallel one: easy PCB layout, lower radiated noise, lower pin count, self-synchronous link, skew compensation.
The maximum number of lanes of the DAC1008D750 is 4 and its maximum serial data rate is 3.
125 Gbps.
The Multiple Device Synchronization (MDS) guarantees a maximum skew of one output clock period between several DAC devices.
MDS incorporates modes: Master/slave and All slave mode.
2.
Features and benefits „ Dual 10-bit resolution „ 750 Msps maximum update rate „ Selectable 2×, 4× or 8× interpolation filters „ Input data rate up to 312.
5 Msps „ Very low-noise cap-free integrated PLL „ 32-bit programmable NCO frequency „ Four JESD204A serial input lanes „ 1.
8 V and 3.
3 V power supplies „ LVDS compatible clock inputs „ IMD3: 76 dBc; fs = 737.
28 Msps; fo = 140 MHz „ ACPR: 64 dBc; two carriers WCDMA; fs = 737.
28 Msps; fo = 153.
6 MHz „ Typical 1.
26 W power dissipation at 4× interpolation, PLL off and 740 Msps „ Power-down mode and Sleep modes „ Differential scalable...


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