(CY7C131xAV18) 18-Mb QDRTM-II SRAM 4-Word Burst Architecture
Description
PRELIMINARY
CY7C1311AV18 CY7C1313AV18 CY7C1315AV18
18-Mb QDR™-II SRAM 4-Word Burst Architecture
Features
Separate Independent Read and Write Data Ports — Supports concurrent transactions 250-MHz Clock for High Bandwidth 4-Word Burst for reducing address bus frequency Double Data Rate (DDR) interfaces on both Read and Write Ports (data transferred a...
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