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H5TC1G83BFR-xxA

Hynix Semiconductor
Part Number H5TC1G83BFR-xxA
Manufacturer Hynix Semiconductor
Description 1Gb DDR3L SDRAM
Published Jul 29, 2013
Detailed Description 1Gb DDR3L SDRAM 1Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC1G43BFR-xxA H5TC1G83BFR-xxA H5TC1G63BFR-xx...
Datasheet PDF File H5TC1G83BFR-xxA PDF File

H5TC1G83BFR-xxA
H5TC1G83BFR-xxA


Overview
1Gb DDR3L SDRAM 1Gb DDR3L SDRAM Lead-Free&Halogen-Free (RoHS Compliant) H5TC1G43BFR-xxA H5TC1G83BFR-xxA H5TC1G63BFR-xxA http://www.
DataSheet4U.
com/ *Hynix Semiconductor reserves the right to change products or specifications without notice Rev.
0.
1 / Nov.
2009 1 Revision History Revision No.
0.
1 History Initial Release Draft Date Nov.
2009 Remark Preliminary http://www.
DataSheet4U.
com/ Rev.
0.
1 / Nov.
2009 2 Description The H5TC1G43BFR-xxA, H5TC1G83BFR-xxA and H5TC1G63BFR-xxA are a 1Gb low power Double Data Rate III (DDR3L) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density, high bandwidth and low power operation at 1.
35V.
Hynix DDR3L SDRAM provides backward compatibility with the 1.
5V DDR3 based environment without any changes.
(Please refer to the SPD information for details.
) Hynix 1Gb DDR3L SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock.
While all addresses and control inputs are latched on the rising edges of the clock (falling edges of the clock), data, data strobes and write data masks inputs are sampled on both rising and falling edges of it.
The data paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Device Features and Ordering Information FEATURES • VDD=VDDQ=1.
35V + 0.
100 / - 0.
067V • Fully differential clock inputs (CK, CK) operation • Differential Data Strobe (DQS, DQS) • On chip DLL align DQ, DQS and DQS transition with CK transition • DM masks write data-in at the both rising and falling edges of the data strobe • All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock • Programmable CAS latency 6, 7, 8, 9, 10 supported • Programmable additive latency 0, CL-1, and CL-2 supported • Programmable CAS Write latency (CWL) = 5, 6, 7 • Programmable burst length 4/8 with both nibble sequential and interleave mode • BL switch on the fly • 8banks • Average Refr...



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