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DSP32C-M4

Lucent Technologies
Part Number DSP32C-M4
Manufacturer Lucent Technologies
Description Digital Signal Processor
Published Jul 22, 2014
Detailed Description Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Products Affected This advisory is effective for issu...
Datasheet PDF File DSP32C-M4 PDF File

DSP32C-M4
DSP32C-M4


Overview
Data Sheet Addendum November 1996 DSP32C Digital Signal Processor Products Affected This advisory is effective for issue 5 of the DSP32C.
Issue 5 devices are identified by a device code of the form DSP32C-X35 (where X is replaced by R or F).
The design consideration involves external writes to and reads from the parallel data register (PDR) with a system clock greater than 66 MHz.
Problem Resolution PEN, PWN, and PGN may be synchronized with the DSP clock to eliminate this potential alignment problem.
Figure 1 illustrates a circuit that may be used to synchronize these inputs.
Figure 2 shows the associated timing.
The synchronization circuit delays the rise and fall points of PEN, PWN, and PGN.
This added delay is equal to the maximum time of tCKOHCKOH + the cp to Q propagation delay of the F74 (tPLH or tPHL).
For an 80 MHz CKI, the maximum delay would be 12.
5 ns + the cp to Q delay of the F74.
Subsequently, the user must ensure that other timing specifications listed in Table 1 and Ta...



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