DatasheetsPDF.com

IDT5P49EE802

Part Number	IDT5P49EE802
Manufacturer	Integrated Device Technology
Description	LOW POWER CLOCK GENERATOR
Published	Aug 21, 2014
Detailed Description	PRELIMINARY DATASHEET VERSACLOCK® LOW POWER CLOCK GENERATOR Description The IDT5P49EE802 is a programmable clock genera...
Datasheet	IDT5P49EE802 PDF File

Overview

PRELIMINARY DATASHEET VERSACLOCK® LOW POWER CLOCK GENERATOR Description The IDT5P49EE802 is a programmable clock generator intended for low power, battery operated consumer applications.
There are four internal PLLs, each individually programmable, allowing for up to eight differrent output frequencies.
The frequencies are generated from a single reference clock.
The reference clock can come from either a TCXO or fundamental mode crystal.
An additional 32kHz crystal oscillator is available to provide a real time clock or non-critical performance MHz processor clock.
The IDT5P49EE802 can be programmed through the use of the I2C interfaces.
The programming interface enables the device to be programmed when it is in normal operation or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up.
Each of the four PLLs has an 8-bit reference divider and a 11-bit feedback divider.
This allows the user to generate four unique non-integer-related frequencies.
The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application.
For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation.
Spread spectrum generation is supported on one of the PLLs.
Spread spectrum generation is supported on one of the PLLs.
The device is specifically designed to work with display applications to ensure that the spread profile remains consistent for each HSYNC in order to reduce ROW noise.
It also may operate in standard spread sepctrum mode.
There are total six 8-bit output dividers.
Outputs are LVCMOS.
The outputs are connected to the PLLs via the switch matrix.
The switch matrix allows the user to route the PLL outputs to any output bank.
This feature can be used to simplify and optimize the board layout.
In addition, each output's slew rate and enable/disable function can be programm...

Similar Datasheet

IDT5P49EE801 LOW POWER CLOCK GENERATOR - Integrated Device Technology
IDT5P49EE802 LOW POWER CLOCK GENERATOR - Integrated Device Technology

@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)