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FE1.1S

JFD
Part Number FE1.1S
Manufacturer JFD
Description USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER
Published Aug 18, 2015
Detailed Description USB 2.0 4-Port Hub Data Sheet Rev. 1.0 www.jfd-ic.com FE1.1S USB 2.0 HIGH SPEED 4-PORT HUB CONTROLLER ________________...
Datasheet PDF File FE1.1S PDF File

FE1.1S
FE1.1S

Overview
USB 2.
0 4-Port Hub Data Sheet Rev.
1.
0 www.
jfd-ic.
com FE1.
1S USB 2.
0 HIGH SPEED 4-PORT HUB CONTROLLER _______________________Data Sheet_______________________ INTRODUCTION The FE1.
1s is a highly integrated, high quality, high performance, low power consumption, yet low cost solution for USB 2.
0 High Speed 4-Port Hub.
It adopts Single Transaction Translator (STT) architecture to be more cost effective.
Six, instead of two, non-periodic transaction buffers are used to minimize potential traffic jamming.
The whole design is based on state-machinecontrol to reduce the response delay time; no micro controller is used in this chip.
To guarantee high quality, the whole chip is covered by Test Scan Chain – even on the high speed (480MHz) modules, so that all the logic components could be fully tested before shipping.
Special Build-In-Self-Test mode is designed to exercise all high, full, and low speed Analog Front End (AFE) components on the packaging and testing stages as well.
Low power consumption is achieved by using 0.
18μm technology and comprehensive power/clock control mechanism.
Most part of the chip will not be clocked unless needed.
FEATURES  Fully compliant with Universal Serial Bus Specification Revision 2.
0 (USB 2.
0); □ Upstream facing port supports HighSpeed (480MHz) and Full-Speed (12MHz) modes; □ 4 downstream facing ports support High-Speed (480MHz), Full-Speed (12MHz), and Low-Speed (1.
5MHz) modes;  Integrated USB 2.
0 Transceivers;  Integrated upstream 1.
5KΩ pull-up, downstream 15KΩ pull-down, and serial resisters;  Integrated 5V to 3.
3V and 1.
8V regulator.
 Integrated Power-On-Reset circuit;  Integrated 12MHz Oscillator with feedback resister, and crystal load capacitance;  Integrated 12MHz-to-480MHz Phase Lock Loop (PLL);  Single Transaction Translator (STT) – □ One TT for all downstream ports; □ The TT could handle 64 periodic Start- Split transactions, 32 periodic Complete-Split transactions, and 6 none-periodic transactions;  Automatic se...


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