CY62146E

CY62146CV18 : of read and write modes. The CY62146CV18 is available in a 48-Ball FBGA package. Functional Description The CY62146CV18 is a high-performance CMOS static RAM organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Logic Block Diagram DATA IN DRIVERS A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array 2048 x 2048 SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation Document #: 38-05010 Rev..

CY62146CV30 : of Read and Write modes. The CY62146CV30 is available in 48-ball FBGA packaging. Functional Description The CY62146CV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL™) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K × 16 RAM Array 2048 × 2048 SENSE AMPS I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER BHE WE CE OE BLE Cypress Semiconductor Corporation Document #: 38-05203.

CY62146DV30 : of read and write modes. The CY62146DV30 is available in a 48-ball VFBGA, 44-pin TSOPII packages. Functional Description[1] The CY62146DV30 is a high-performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life™ (MoBL) in portable applications such as cellular telephones. The device also has Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array SENSE AMPS I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A11 A12 A13 A14 A15 A16 Note: 1. For best practice recommendations, please refer to the Cypress app.

CY62146ESL : of read and write modes. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Functional Description The CY62146ESL is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that reduces power consumption when addresses are not toggling. Placing the device into standby Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K x 16 RAM Array SENSE AMPS .

CY62146EV30 : of read and write modes. Functional Description [1] The CY62146EV30 is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features advanced circuit design to provide ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly Product Portfolio Power Dissipation Product VCC Range (V) Min CY62146EV30LL 2.2 Typ [2] 3.0 Max 3.6 45 ns Speed (ns) Typ [2] 2 Operating ICC (mA) f = 1 MHz Max 2.5 f = fmax Typ [2] 15 Max 20 Standby ISB2 (µA) Typ [2] 1 Max 7 Notes: 1. For best practice recommendations, please refer to the Cyp.

CY62146G : CY62146G/CY62146GE and CY62146GSL/CY62146GESL are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62146GE/CY62146GESL device includes an ERR pin that signals an error-detection and correction event during a read cycle. The CY62146GSL/CY62146GESL[1] device supports a wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as low and CE2 as HIGH. Data writes are performed by asserting the Write .

CY62146G-MoBL : CY62146G is high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Device is accessed by asserting the chip enable (CE) input LOW. Data writes are performed by asserting the Write Enable (WE) input LOW, while providing the data on I/O0 through I/O15 and address on A0 through A17 pins. The Byte High Enable (BHE) and Byte Low Enable (BLE) inputs control write operations to the upper and lower bytes of the specified memory location. BHE controls I/O8 through I/O15 and BLE controls I/O0 through I/O7. Data reads are performed by asserting the Output Enable (OE) input and providing the required address on the address lines. Read data is accessible on the I/O lines (I/O0 through I/O.

CY62146GE : CY62146G/CY62146GE and CY62146GSL/CY62146GESL are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62146GE/CY62146GESL device includes an ERR pin that signals an error-detection and correction event during a read cycle. The CY62146GSL/CY62146GESL[1] device supports a wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as low and CE2 as HIGH. Data writes are performed by asserting the Write .

CY62146GESL : CY62146G/CY62146GE and CY62146GSL/CY62146GESL are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62146GE/CY62146GESL device includes an ERR pin that signals an error-detection and correction event during a read cycle. The CY62146GSL/CY62146GESL[1] device supports a wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as low and CE2 as HIGH. Data writes are performed by asserting the Write .

CY62146GN : The CY62146GN is a high performance CMOS static RAM organized as 256K words by 16 bits. This device features an advanced circuit design designed to provide an ultra low active current. Ultra low active current is ideal for providing More Battery Life (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 80 percent when addresses are not toggling.The device can also be put into standby mode reducing power consumption by more than 99 percent when deselected (CE HIGH). The input and output pins (I/O0 through I/O15) are placed in a high impedance state when the device is deselected (CE H.

CY62146GSL : CY62146G/CY62146GE and CY62146GSL/CY62146GESL are high-performance CMOS low-power (MoBL) SRAM devices with embedded ECC. Both devices are offered in single and dual chip enable options and in multiple pin configurations. The CY62146GE/CY62146GESL device includes an ERR pin that signals an error-detection and correction event during a read cycle. The CY62146GSL/CY62146GESL[1] device supports a wide voltage range of 2.2 V–3.6 V and 4.5 V–5.5 V. Devices with a single chip enable input are accessed by asserting the chip enable (CE) input LOW. Dual chip enable devices are accessed by asserting both chip enable inputs – CE1 as low and CE2 as HIGH. Data writes are performed by asserting the Write .

CY62146VLL-70ZI : of read and write modes. Functional Description[1] The CY62146V is a high-performance CMOS static RAM organized as 256K words by 16 bits. These devices feature advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life® (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 99% when addresses are not toggling. The device can also be put into standby mode when Logic Block Diagram DATA IN DRIVERS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER 256K × 16 RAM Array 2048 × 2048 SENSE AMPS I/O0 – I/O7 I/O8 – I/O15 COLUMN DECODER BHE WE CE O.