IS61QDB42M18A IS61QDB41M36A 2Mx18, 1Mx36 36Mb QUAD (Burst 4) SYNCHRONOUS SRAM FEATURES DESCRIPTION APRIL 2016  1Mx36 and 2Mx18 configuration available.
 On-chip Delay-Locked Loop (DLL) for wide data valid window.
 Separate independent read and write ports with concurrent read and write operations.
 Synchronous pipeline read with late write operation.
 Double Data Rate (DDR) interface for read and write input ports.
 1.
5 cycle read latency.
 Fixed 4-bit burst for read and write operations.
 Clock stop support.
 Two input clocks (K and K#) for address and control registering at rising edges only.
 Two output clocks (C and C#) for data output control.
 Two echo clocks (CQ and CQ#...

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