36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM
IS61DDB22M18A IS61DDB21M36A 2Mx18, 1Mx36 36Mb DDR-II (Burst 2) CIO SYNCHRONOUS SRAM JANUARY 2015 FEATURES 1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid window. Common I/O read and write ports. Synchronous pipeline read with self-timed late write operation. Double Data Rate (DDR) interface for read an...
Integrated Silicon Solution