DatasheetsPDF.com

IS61DDB21M36

Integrated Silicon Solution
Part Number IS61DDB21M36
Manufacturer Integrated Silicon Solution
Description DDR-II (Burst of 2) CIO Synchronous SRAMs
Published Jul 25, 2016
Detailed Description 36 Mb (1M x 36. & 2M x 18) ISSIDDR-II (Burst of 2) CIO Synchronous SRAMs ® Features • 1M x 36 or 2M x 18. • On-chip de...
Datasheet PDF File IS61DDB21M36 PDF File

IS61DDB21M36
IS61DDB21M36

Overview
36 Mb (1M x 36.
& 2M x 18) ISSIDDR-II (Burst of 2) CIO Synchronous SRAMs ® Features • 1M x 36 or 2M x 18.
• On-chip delay-locked loop (DLL) for wide data valid window.
• Common data input/output bus.
• Synchronous pipeline read with self-timed late write operation.
• Double data rate (DDR-II) interface for read and write input ports.
• Fixed 2-bit burst for read and write operations.
• Clock stop support.
• Two input clocks (K and K) for address and control registering at rising edges only.
• Two input clocks (C and C) for data output control.
May 2005 • Two echo clocks (CQ and CQ) that are delivered simultaneously with data.
• +1.
8V core power supply and 1.
5, 1.
8V VDDQ, used with 0.
75, 0.
9V VREF.
• HSTL input and output levels.
• Registered addresses, write and read controls, byte writes, data in, and data outputs.
• Full data coherency.
• Boundary scan using limited set of JTAG 1149.
1 functions.
• Byte write capability.
• Fine ball grid array (FBGA) package - 15mm x 17mm body size...


Similar Datasheet


@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site. (Privacy Policy & Contact)