Standard Products UT8SF2M40 80Megabit Flow-thru SSRAM Preliminary Datasheet www.
aeroflex.
com/memories April 2015 FEATURES  Synchronous SRAM organized as 2Meg words x 40bit  Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations  Supports 40MHz to 80MHz bus operations  Internally self-timed output buffer control eliminates the need for synchronous output enable  Registered inputs and outputs for flow-thru operation  Single 2.
5V to 3.
3V supply  Clock-to-output time - Clk to Q = 12ns  Clock Enable (CEN) pin to enable clock and suspend operation  Synchronous self-timed writes  Three Chip Enables (CS0, CS1, CS2) for simple depth expansion ...

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