CD40102BMS CD40103BMS December 1992 CMOS 8-Stage Presettable Synchronous Down Counters Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero.
The CD40102BMS is configured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter.
Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously.
All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic.
In normal operation, the counter is decremented by one count on each pos...

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