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CD40103BMS

Part Number	CD40103BMS
Manufacturer	Intersil Corporation
Description	CMOS 8-Stage Presettable Synchronous Down Counters
Published	Mar 23, 2005
Detailed Description	CD40102BMS CD40103BMS December 1992 CMOS 8-Stage Presettable Synchronous Down Counters Description CD40102BMS and CD401...
Datasheet	CD40103BMS PDF File

Overview

CD40102BMS CD40103BMS December 1992 CMOS 8-Stage Presettable Synchronous Down Counters Description CD40102BMS and CD40103BMS consist of an 8-stage synchronous down counter with a single output which is active when the internal count is zero.
The CD40102BMS is conﬁgured as two cascaded 4-bit BCD counters, and the CD40103BMS contains a single 8-bit binary counter.
Each type has control inputs for enabling or disabling the clock, for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously.
All control inputs and the CARRY-OUT/ZERO-DETECT output are active-low logic.
In normal operation, the counter is decremented by one count on each positive transition of the CLOCK.
Counting is inhibited when the CARRY-IN/COUNTER ENABLE (CI/CE) inputs is high.
The CARRY-OUT/ZERO-DETECT (CO/ZD) output goes low when the count reaches zero if the CI/CE input is low, and remains low for one full clock period.
When the SYNCHRONOUS PRESET-ENABLE (SPE) i...

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