12 LVDS/24 CMOS Output Clock Generator
Data Sheet FEATURES Low phase noise, phase-locked loop (PLL) Supports external 3.3 V/5 V voltage controlled oscillator (VCO)/VCXO to 2.4 GHz 1 differential or 2 single-ended reference inputs Accepts CMOS, LVPECL, or LVDS references to 250 MHz Accepts 16.62 MHz to 33.3 MHz crystal for reference input Optional reference clock doubler Reference monitoring capab...
Analog Devices