Part Number
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74LS112A |
Manufacturer
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Fairchild Semiconductor |
Description
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Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop |
Published
|
Jan 7, 2017 |
Detailed Description
|
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August...
|
Datasheet
|
74LS112A
|
Overview
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
August 1986 Revised March 2000
DM74LS112A
Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs
General Description
This device contains two independent negative-edge-triggered J-K flip-flops with complementary outputs.
The J and K data is processed by the flip-flop on the falling edge of the clock pulse.
The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse.
Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting t...
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