Data Sheet FEATURES Low output skew 30 ps (typical) Distributes one differential clock input to 10 LVDS clock outputs Programmable—one of two differential clock inputs can be selected (CLK0, CLK1) and individual differential clock outputs enabled/disabled Signaling rate up to 1.
1 GHz (typical) 2.
375 V to 2.
625 V power supply range ±100 mV differential input threshold Input common-mode range from rail-to-rail I/O pins fail-safe during power-down: VDD = 0 V Available in 32-lead LFCSP and LQFP packages Industrial operating temperature range: −40°C to +85°C APPLICATIONS Clock distribution networks GENERAL DESCRIPTION The ADN4670 is a low voltage differential signaling (LVDS) clock driver that e...

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