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ADN4605

Analog Devices
Part Number ADN4605
Manufacturer Analog Devices
Description 4.25 Gbps 40 x 40 Digital Crosspoint Switch
Published Jul 6, 2011
Detailed Description Data Sheet FEATURES DC to 4.25 Gbps per port NRZ data rate Adjustable receive equalization 3 dB, 6 dB, or 12 dB boost Co...
Datasheet PDF File ADN4605 PDF File

ADN4605
ADN4605

Overview
Data Sheet FEATURES DC to 4.
25 Gbps per port NRZ data rate Adjustable receive equalization 3 dB, 6 dB, or 12 dB boost Compensates over 40 inches of FR4 at 4.
25 Gbps Adjustable transmit preemphasis/deemphasis Programmable boost and output level Compensates over 40 inches of FR4 at 4.
25 Gbps Low power 105 mW per channel at 2.
5 V (400 mV p-p differential output level swing) 40 × 40, fully differential, nonblocking array Double rank connection programming with dual maps Low jitter, typically <25 ps Flexible 2.
5 V to 3.
3 V supply range DC- or ac-coupled differential PECL/CML inputs Differential CML outputs Per-lane polarity inversion for routing ease 50 Ω on-chip I/O termination with disable feature Supports 8b10b, scrambled or uncoded NRZ data Serial (IC slave or SPI) control interface Parallel control interface APPLICATIONS Digital video (HDMI, DVI, DisplayPort, 3G/HD/SD-SDI) Fiber optic network switching High speed serial backplane routing to OC-48 with FEC XAUI, 4x Fibre Channel, Infiniband®, and GbE over backplane Data storage networks GENERAL DESCRIPTION The ADN4605 is a 40 × 40 asynchronous, protocol agnostic, digital crosspoint switch, with 40 differential PECL/CMLcompatible inputs and 40 differential programmable CML outputs.
The ADN4605 is optimized for NRZ signaling with data rates of up to 4.
25 Gbps per port.
Each port offers adjustable levels of input equalization, programmable output swing, and output preemphasis/deemphasis.
4.
25 Gbps 40 × 40 Digital Crosspoint Switch ADN4605 FUNCTIONAL BLOCK DIAGRAM DVCC VCC IP[39:0] VTTIA, VTTIB IN[39:0] Rx Tx EQ 40 × 40 SWITCH MATRIX PREEMPHASIS OP[39:0] VTTOA, VTTOB ON[39:0] EQUALIZATION SETTINGS CONNECTION MAP 1 CONNECTION MAP 0 OUTPUT LEVEL SETTINGS PREEMPHASIS LEVEL SETTINGS RESET SER/PAR I2C/SPI (UPDATE) CS SCL/SCK/ WE SDI/RE PARALLEL/SERIA L CONTROL LOGIC INTERFACE VEE Figure 1.
ADN4605 DATA[0]/ SDA/SDO DATA[1] (UPDATE) DATA[7:2] ADDR[7:0] 09796-001 The ADN4605 nonblocking switch core implemen...


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