HD74AC195 4-bit Parallel-Access Shift Register REJ03D0260–0200Z (Previous ADE-205-380 (Z)) Rev.
2.
00 Jul.
16.
2004 Description This shift register features parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear.
This shift register can operate in two modes: Parallel load; Shift from Q0 towards Q3.
Parallel loading is accomplished by applying the four bits of data, and taking the PE Input low.
The data is loaded into the associated flip-flops and appears at the outputs after the positive transition of the CP input.
During parallel loading, serial data flow is inhibited.
Serial shifting occurs synchronously when the PE input is high.
Serial ...

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